1. Related Invention
This invention is related to "Improved Phase-Locked Loop Control for Reading Data Off Storage Media" by Brian G. Cleveland, Ser. No. 07/183,843, filed Apr. 20, 1988.
2. Field of the Invention
The field of this invention pertains to phase-locked loop controls for reading data from storage media and, in particular, to phase-locked loop controls having improved dead track acquisition during reading of data from high density media such as the IBM 3480 cartridge storage system.
3. Discussion of Prior Art
It is conventional in high performance disk, tape or optical products to employ a phase-locked loop (PLL) in the read channels. The phase-locked loop control functions to track speed variations of the incoming data read from the media to insure accurate reading of data.
An example of a conventional tape product that incorporates a phase-locked loop control is shown in FIG. 1. In FIG. 1, a storage media 10 such as the IBM 3480 cartridge is read by a tape head 20 which delivers output signals through an automatic gain control circuit (AGC) 30. The signals from the automatic gain control circuit 30 enter a filter and equalizer circuit 40 which filters the signal and provides equalization thereto. The signals are then delivered to a peak detector 50 which for every peak delivers a digital value representing a "digital one" that was previously written on the media. The peak detector delivers the signal to a conventional phase-locked loop circuit 60 which, as mentioned, tracks speed variations in the incoming data on storage media 10. The data from the phase-locked loop 60 is delivered to a conventional data separator 70 and error correction circuit 80 for delivery as digital bytes of data information 90 into the system. The dead track detector circuit 100 in cooperation with the error correction circuit 80 conventionally ascertains whether a data track in the media 10 has been in error for a certain length such as eight frames or more, and if so, ignores that track for a predetermined number of frames. In the IBM approach, every 72nd frame of a data block has RESYNC bytes (i.e., Frame 72) which do not form part of the customer's data.
Once a particular track has been designated "dead" by circuit 100, the error correction circuit 80 ignores the data read from that track and proceeds to correct it according to conventional error correction techniques. During this time, the phase-locked loop 60 still continues to lock to the "dead" track and, as the RESYNC frame approaches, the SYNC detector 95 looks for the unique RESYNC bytes (i.e., in the IBM system: 100010001). Upon detection of RESYNC, the track is returned to the normal mode (i.e., Not Dead) and tries to read the actual data. If the track is performing properly, the normal mode is maintained. If not, the track is again designated dead. This process repeats for each RESYNC frame in the customer's data. In FIG. 2, the conventional phase-locked loop circuit 60 is shown to include a data selector which obtains the incoming data from the peak detector 50. The data selector circuit 200 is conventional. The output of the data selector is delivered into the phase detector 210. Phase detector 210 compares the incoming signal on line 202 to the clock on line 232 and if there is any difference between the phase of the clock and the phase of the data on line 202, a charge pump 220 is selectively activated. For example, if the data pulse precedes the clock pulse, this is an early phase error and lead 212 becomes activated to cause the charge pump circuit 220 to deliver more current into the filter 225 which is converted to a voltage. This causes the voltage controlled oscillator (VCO) 230 to increase frequency in order to obtain a phase match. Likewise, if the data on lead 202 follows the clock pulse, a late signal is delivered over lead 214 to the charge pump 220 to cause the frequency of the voltage control oscillator 230 to slow down. In a predetermined number of clock cycles, the phase-locked loop circuit 60 is in synchronism with the data. An example of a prior phase-locked loop approach is found in U.S. Pat. No. 4,068,198.
Variations in the frequency of the signal on lead 202 can be due to a number of things including defects in the media 10 which could cause dropouts or missing pulses, speed variations, and tape flying irregularities. The voltage controlled oscillator 230 is typically a variable 1.95 MHz clock for the IBM 3480 environment.
In FIG. 3, the prior art data format for the IBM 3480 high density tape storage sub-system is set forth showing an interlock gap (IBG) 300 followed by a preamble field (PRE) 310 comprising nine to thirteen frames of all "ones." Following the preamble field 310 is a synchronization (SYNC) field 320 which normally is two frames and which precedes a variable length customer data block (DB) 330. Every 72nd frame 340 of the data block 330 has the RESYNC field as discussed above. Other special purpose frames are not shown.
The phase-locked loop 60 operates in a high gain mode (HGM) during the preamble frames 310. During this mode of operation, the phase detector 210 matches the phase for each "one" read in the preamble. In the high gain mode, the phase-locked loop control 60 synchronizes the oscillator 230 with the frequency of the incoming data generally within two to five frames. After seven frames of the preamble frames 300, the phase-locked loop 60 enters the low gain mode (LGM) which provides phase comparisons only on the edges of data "ones."
As mentioned, proper synchronization is not always successful. For example, defects in the magnetic media can obscure the data. Tape drives may also exhibit varying degrees of skew across the head so that the preamble is not aligning with all tracks simultaneously. Furthermore, the tape could flutter across the head and thereby obscure the data. During the inter block gap (IBG), the phase-locked loop control 60 is idle.
4. Statement of Problem
A problem arises with the prior approach of FIGS. 1 through 3 when defects such as corrupt data or frequency variations exist with the actual data on the track so that the PLL 60 loses lock and is unable to recover data from the rest of the data block 330. In such a case, the PLL will not regain lock until a new block of data is read and, therefore, the track will always be dead throughout the entire record length. When the PLL 60 loses lock it is unable to read the RESYNC frames. When this occurs, even though the track may be able to be properly read, with the PLL out of lock, the track will be wrongly termed "dead."
5. Solution
The present invention provides a solution to this problem to better insure the integrity of operation of the phase-locked loop control 60. An oscillator having a frequency fixed to the expected frequency of the storage media (i.e., 1.95 MHz for the IBM 3480 media) is used as an input to the PLL when a track has been designated "dead." The PLL 60 then locks onto this separate oscillator input and maintains lock during reading of the "dead" track. As the RESYNC frame is approached, the data selector is activated to read the track with the full assurance that the PLL is properly locked in.